Application specific integrated circuits (ASICs), for example, used in sensors, have often a low-power internal voltage regulator to regulate the power supply of circuit blocks that are permanently switched on. Typically two different types of voltage regulators are used which are closed-loop system or open-loop topologies. Each type has specific advantages and disadvantages. For example, closed-loop systems can be designed to have a relatively stable feed-back loop by use of small output capacitor. When the output capacitor of the closed-loop system is relatively small and when the load is switching and is drawing sharp and short spikes from the voltage regulated, the regulated output voltage will be severely disturbed and will gently recover to its regulated value after the load current spikes. This requires a large output decoupling capacitor to smoothen the fast load current spikes. It is necessary that the decoupling capacitor is within the range allowed by the design. The open-loop topologies are less prone to stability issues because a driving transistor that provides the regulated voltage is placed outside the feedback loop, however, the provided regulated voltage by the open-loop voltage regulators is sensitive to the value of the load current.
When, for example, a sensor is provided with such an internal voltage regulator, it is required that the voltage regulator is able to provide a regulated voltage, even when the supply voltage of the voltage regulator becomes very close to the regulated voltage. This is the so-termed low drop-out voltage operational condition and a voltage regulator which is able to correct operate under such an operational condition is termed a low drop-out voltage regulator. When a sensor is provided with, for example, a battery, a low drop-out voltage regulator ensures that the sensor is able to operate as long as possible even when the voltage provided by the battery drops to a level close to the regulated voltage because of exhaustion of the battery.
A known solution for obtaining a low drop-out behavior is the use of pull-up circuits. The function of a pull-up circuits is to prevent that the regulated output voltage drops below a minimum required regulated voltage as the result of a drop of the supply voltage. When the supply voltage becomes close to the minimum required regulated voltage, a pull-up circuit connects the regulated output voltage directly to the supply voltage to obtain a regulated output voltage that is above a minimum required regulated voltage. In open-loop voltage regulators pull-up circuits are also used to pull-up a voltage of a terminal in the internal feedback loop of the voltage regulator. A pull-up circuit is mainly used in open-loop voltage regulators, because in closed-loop regulators the p-type MOS output transistor already acts like a pull-up circuit when the supply voltage drops near the regulated output voltage.
Applying a pull-up circuit in a feed-back loop of an voltage regulator may lead to stability issues, because, at the moments of time of pulling-up and ending the pulling-up, a voltage suddenly changes.
Published US patent application US2007/159146 discloses a low drop-out (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles' frequency reshaping” are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance is needed to stabilize a regulator. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit.
The cited patent application proposes a variant of the classic Miller compensation for a two stage low drop-out regulator. Thanks to a local feedback within the Miller compensation network, the circuit is more tolerant of variations in load current and load capacitor than conventional topologies. However, since it remains a closed-loop system, the LDO is not unconditionally stable. For very low load current (logic in standby mode) and large load capacitor, the phase margin becomes very poor, unless a minimum sink current (indicated by reference number 518 in FIG. 5 of the cited patent application) is added, which penalizes current consumption. On the other end, for large load current and small load capacitor, a complex pair of poles appear in the transfer function, which again jeopardizes the stability. In conclusion, the published patent application provides some more stability in a closed-loop voltage regulator, but still specific stability issues remain.